PCI Express
The PCIe physical layer
consists of a network of serial interconnects much like twisted pair Ethernet. A single hub with
many pins on the mainboard is used, allowing extensive switching and
parallelism and the serial interconnects (known as lanes) can be grouped to
provide higher bandwidth. This design was chosen because as clock rates
increase, synchronization of parallel connections is hindered by timing skew. PCI-e is just one
example of a general trend away from parallel buses to serial interconnects.
For other examples, see Hyper Transport, Serial ATA, USB, SAS or FireWire. A
multichannel serial design also increases flexibility; slow devices can be
given a single lane with a relatively small number of pins while fast devices
can be given more lanes as necessary up to a maximum of 32.
